CMOS is the dominant technology in almost all VLSI design. CMOS circuits use a combination of p-channel (PMOS) and n-channel (NMOS) metal oxide semiconductor field effect transistors (MOSFETs) to implement logic gates and switches. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. A CMOS logic inverter accomplishes current reduction by complementing every NMOS transistor with a PMOS transistor and connecting both gates and both drains together.
CMOS transmission gates, also known as CMOS analog switches (herein “CMOS switch(es”) often form the interface between analog signals and digital controllers. The internal construction of a typical CMOS switch connects an NMOS in parallel with a PMOS to enable signals to pass in either direction with equal ease. The MOSFETs' sources are connected to each other and their drains are connected to each other. The terminals of the switched conduction path are the sources on one side and the drains on the other side. The switch is controlled by the gate-source voltage of the NMOS and PMOS devices. Whether the n- or p-channel device carries more signal current depends on the ratio of input to output voltage. Because the switch has no preferred direction for current flow, it has no preferred input or output. The typical CMOS switch can only be used if the terminal voltages are within the range of the supply rails.
CMOS switches, especially when used in power applications, often do not get the proper voltage values at their switch terminals to open and close correctly because they are often integrated on VLSI chips with dense digital and analog circuitry. A CMOS device requires control of the gate-to-source voltage to keep it within the maximum limits set by the process specifications which are typically much lower than the maximum limits for drain to source voltage. For example, a high-voltage CMOS switch device may have a drain-source voltage rating of 100 volts, but the maximum gate-source voltage may be only 5 volts. When the CMOS source voltage is not within the range of the supply voltage, some means must be provided to generate the gate voltage necessary to turn on the device. It is also necessary to hold the gate-source voltage to zero when the switch is in the off state. The standard practice in the art is to use charge pumps or level shifters that are used to provide the gate drive for CMOS switches in high voltage applications. The use of charge pumps, level shifters, or similar techniques typically do not provide gate voltage control independent of the polarity of the switch terminal voltages relative to each other and relative to the low voltage power supply rails.
CMOS devices are prone to a parasitic effect known as the parasitic diode of MOSFET, more commonly described as “the body diode”, which causes an unwanted flow/direction of current over the body of the CMOS device, rather than the channel. The body diode is a consequence of the high volume CMOS design. The body diode occurs when a diode forms in the body, source and drain regions. When it is forward biased, it becomes an alternative path for current to flow and most of the current may pass to the body instead of through the channel. When reversed biased, it will develop capacitance due to the inherent nature of the diode. The formation of a parasitic diode (herein “body diode”) can cause a latch-up or circuit failure.
Body diodes occur when using standard CMOS switches. The body diode of the PMOS device will conduct if the voltage on either the source or drain is greater than the positive supply voltage. Likewise, the body diode of the NMOS device will conduct if the voltage on either the source or Drain is less than the negative supply voltage. This is the reason why a standard CMOS switch can only be used if the source and drain terminal voltages are within the range of the supply rails. In a non-isolated CMOS process, the body of the NMOS device is connected to a common P-type silicon substrate. The source and drain of the NMOS are N-type implants on top of the P substrate. The body diodes are formed by the P-N junctions from body-to-drain and body-to-source. The body of the PMOS device is an N-well located on top of the common P-type substrate. In a non-isolated process without SOI and trench isolation, the P substrate is connected to the negative supply rail. Thus, the body of the NMOS device is always connected to the negative supply. The substrate underneath the N-well body of the PMOS device is the same substrate, connected to the negative supply. It is not possible to allow the voltage of the N-well body of the PMOS device to drop below the negative supply voltage without causing the substrate diode to conduct.
There are non-Silicon-On-Insulator processes that advertise isolated devices using a deep Nwell or N buried layer (NBL) that runs under the P-type body of the NMOS device and around the sides. In that case, the body of the NMOS device can be connected to a voltage other than the negative supply voltage, provided that the deep N-well is always biased with a voltage greater than or equal to the body voltage so as to avoid conduction through the P-N junction diode formed by the P body and deep N-well. The deep N-well also has to be biased at a voltage greater than or equal to the negative supply rail to avoid conduction through the diode formed by the P substrate and deep Nwell. The structure of the PMOS device is typically the same as in a non-isolated process. All of those parasitic paths place restrictions on the voltages that can be applied to the deep N and to the CMOS body, drain and source terminals. Hence, there is a need for a bidirectional integrated CMOS switch capable of switching voltages beyond the range of supply and ground potentials. Additionally, there is a need for a means to prevent conduction through the parasitic body diodes of the CMOS switch. The present invention enables switching high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The present invention can operate with high terminal voltages above and below the supply rails, which standard CMOS transmission gates cannot do. The present invention provides the proper gate voltages necessary to operate the switch, regardless of the switch terminal voltages. The present invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices. The present invention can be integrated on the same CMOS chip as other circuitry, eliminating the need for separate TRIAC switches, optocouplers, or other external devices. No charge pumps or high voltage supplies are needed. The present invention provides cost efficiencies because of its efficient integration with other components and its lower failure rate.